library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all;
entity KADAI14 is port ( CLK, RESET : in std_logic; Z : out std_logic_vector(3 downto 0)); end KADAI14;
architecture RTL of KADAI14 is signal DEC : std_logic; signal COUNT : std_logic_vector(3 downto 0); begin process( COUNT, RESET, DEC ) begin if( COUNT = "0000" ) then DEC <= '0'; elsif( RESET='1' ) then DEC <= '0'; elsif( COUNT="1111" ) then DEC <= '1'; elsif( DEC='1' and COUNT="1010" ) then DEC <= '0'; end if; end process;
process( CLK, RESET, DEC ) begin if( RESET = '1' ) then COUNT <= "0000"; elsif( CLK'event and CLK='0' ) then if ( DEC='1' ) then COUNT <= COUNT - 1; else COUNT <= COUNT + 1; end if; end if; end process;